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quad, current - output, serial - input 16 - /14 - bit dacs data sheet ad5544 / ad5554 rev. g document feedback information furnished by anal og devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change wi thout notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9 106, u.s.a. tel: 781.329.4700 ? 2000 C 2013 analog devices, inc. all rights reserved. technical support ww w.analog.com f eatures ad5544 : 16- bit resolution inl of 1 lsb ( b grade ) ad5554 : 14- bit resolution inl of 0.5 lsb ( b grade ) 2 ma full - scale current 20%, with v ref = 10 v 0.9 s settling time to 0.1% 12 mhz multiplying bandwidth midscale g litch of ? 1 nv - s ec m idscale or zero - scale reset 4 separate, 4 - quadrant multiplying reference inputs spi - compatible, 3 - wire interface double - buffered registers enable simultaneous multichannel change internal power - on reset temperature rang e : ? 40c to +125c compa ct 28 - lead ssop and 32- lead lfcsp a pplications automatic test equipment instrumentation digitally controlled calibration f unctional block diag ram i n p u t r e gis t e r r 1 6 da c a r e gis t e r r 2 : 4 d e c o d e dac a b c d p o w e r - o n r ese t d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 1 0 d 1 1 d 1 2 d 1 3 d 1 4 d 1 5 a 0 a 1 e n v d d r f b a i o u t a a g n d a a g n d f v s s l da c m s b r s d g n d c l k c s s d i s d o v r e f a b c r f b b i o u t b a g n d b r f b c i o u t c a g n d c r f b d i o u t d a g n d d ad 554 4 i n p u t r e gis t e r r i n p u t r e gis t e r r i n p u t r e gis t e r r dac b r e gis t e r r dac c r e gis t e r r dac d r e gis t e r r d da c a dac b dac d dac c 00943-001 figure 1. general description the ad5 544/ ad5554 quad, 16 - /14 - bit, current output, digital - to - analog converters (dacs) are designed to operate from a 2.7 v to 5.5 v supply range. the applied external reference input voltage (v ref x) determines the full - scale output current. integrated feedback resistors (r fb ) provide temperature - tracking, full - scale voltage outputs when combined with an external i - to - v precision amplifier. a double - buffered serial data interface offers high speed, 3 - wire, spi - and microcontroller - compatible inputs using serial data in (sdi), a chip select ( cs ), and clock (clk) signals. in addition, a serial data out pin (sdo) allows for daisy - chaining when multiple packages are used. a common, level - sensitive, loa d dac strobe ( ldac ) input allows the simultaneous update of all dac outputs from previously loaded input registers. additionally, an internal power - on reset forces the output voltage to 0 at system turn - on. the msb pin allows system reset assertion ( rs ) to force all registers to zero code when msb = 0 or to half - scale code when msb = 1. the ad5544 is packaged in the compact 28 - lead ssop and 32 - lead lfcsp. the ad5554 is packed in the compact 28 - lead ssop. the ev - ad5544/45sdz is avai lable for evaluating dac perfor - mance. for more information, see the ug - 285 evaluation board user guide. 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 0 10,000 30,000 50,000 70,000 00943-002 inl error (lsb) code 20,000 40,000 60,000 figure 2. ad55 44 inl vs. code plot (t a = 25c)
ad5544/ad5554 data sheet rev. g | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ad5544 electrical characteristics ............................................. 3 ad5554 e lectrical c haracteristics ............................................. 4 timing diagrams .......................................................................... 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance charac teristics ........................................... 10 theory of operation ...................................................................... 13 digital - to - analog converter (dac) ....................................... 13 serial data interface ....................................................................... 15 truth tables ................................................................................. 16 power - on reset .......................................................................... 17 esd protection circuits ............................................................ 17 power supply sequence ............................................................. 17 layout and power supply bypassing ....................................... 18 grounding ................................................................................... 18 applications information .............................................................. 19 reference selection .................................................................... 19 amplifier selection .................................................................... 19 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 22 r e vision h istory 5 /13 rev. f to rev. g changes to general description section ...................................... 1 deleted evaluation board for the ad5544 section and figure 30 to figure 35; renumbered sequentially ..................... 22 updated outline dimensions ....................................................... 2 1 changes to ordering guide .......................................................... 2 2 1 /12 rev. e to rev. f changes to figure 1 .......................................................................... 1 added figure 18; renumbered sequentially .............................. 1 1 changes to evaluation board schematics section ..................... 22 6 /1 1 rev. d to rev. e added 32 - lead lfcsp .................................................. throughout changes to table 1 , supply characteristics parameters .............. 3 changes to table 2, supp ly characteristics parameters .............. 5 added figure 6, renumbered subsequent figures, changes to table 4 ............................................................................................ 7 changed applications section to applications information section, added reference selection and amplifier selection section s ............................................................................................ 19 added evaluation board for t he ad5544 section ..................... 21 updated outline dimensions ....................................................... 17 changes to ordering guide .......................................................... 18 9/09 rev. c to rev. d changes to features section ............................................................ 1 changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 4 changes to figure 12 ........................................................................ 9 changes to figure 19 ...................................................................... 10 changes to table 8 and table 9 ..................................................... 13 c hanges to ordering guide .......................................................... 16 8/09 rev. b to rev. c change to table 1 .............................................................................. 3 change to table 2 .............................................................................. 4 8 /09 rev. a to rev. b changes to features section ............................................................ 1 changes to figure 2 ........................................................................... 1 changes to table 1 ............................................................................. 3 changes to table 2 ............................................................................. 4 moved timing diagram ................................................................... 5 added figure 4 ; renumbered sequentially ................................... 5 change to table 3 .............................................................................. 6 changes to table 4 ............................................................................. 7 changes to typical perfo rmance characteristics section ........... 8 changes to figure 19 ...................................................................... 10 moved table 5, table 6, and table 7 ............................................ 12 moved truth tables section ......................................................... 13 deleted figure 27; renumbered sequentially ............................ 14 upd ated outline dimensions ....................................................... 16 changes to ordering guide .......................................................... 16 12/04 rev. 0 to rev. a updated format .................................................................. universal change to electrical characteristics tables ................................... 4 change to pin description table ................................................. 10 addition of power supply sequence section .............................. 19 addition of layout and pow er supply bypassing section ........ 19 addition of grounding section .................................................... 19 addition of figure 32 ..................................................................... 19 4/00 revision 0: initial version
data sheet ad5544/ad5554 rev. g | page 3 of 24 specifications ad5544 electrical character istics v dd = 2.7 v to 5 .5 v , v ss = 0 v, i out x = virtual gnd, a gnd x = 0 v, v ref a = v ref b = v ref c = v ref d = 10 v, t a = full operating temperature range of ?40c to +125c , unless otherwise noted. table 1 . parameter symbol test condition/comments min typ max unit static performance 1 resolution n 1 lsb = v ref x /2 16 = 153 v when v ref = 10 v 16 bits relative accuracy inl a d5544brsz 1 lsb ad5544arsz 2 lsb ad5544bcpz 1 lsb ad5544acpz -1 4 lsb differential nonlinearity dnl ad5544brsz 1 lsb ad5544arsz 1.5 lsb ad5544bcpz 1 lsb ad5544acpz -1 1 lsb output leakage current i out x data = 0x000 0, t a = 25c 10 na data = 0x0000, t a = 8 5c 20 na full - scale gain error g fse data = 0xffff 0.75 3 mv full - scale tempco 2 tcv fs 1 ppm/c feedback resistor r fb x v dd = 5 v 4 6 8 k ? reference input v ref x range v ref x ? 15 +15 v input resistance r ref x 4 6 8 k ? input resistance match r ref x channel - to - channel 0.35 % input capacitance 2 c ref x 5 pf analog output output current i ou t x data = 0xffff 1.25 2.5 ma output capacitance 2 c out x code dependent 35 pf logic input and output logic input low voltage v il 0.8 v logic input high voltage v ih 2.4 v input leakage current i il 1 a input capacitance 2 c il 10 pf logic output low voltage v ol i ol = 1.6 ma 0.4 v logic output high voltage v oh i oh = 100 a 4 v interface timing 2 , 3 clock width high t ch 25 ns clock width low t cl 25 ns cs to clock setup t css 0 ns clock to cs hold t csh 25 ns clock to sdo propagation delay t pd 2 20 ns load dac pulse width t ldac 25 ns data setup t ds 20 ns data hold t dh 20 ns load setup t lds 5 ns load hold t ldh 25 ns supply characteristics power supply range v dd range 2.7 5.5 v positive supply current i dd logic inputs = 0 v 5 a negative supply current i ss logic inputs = 0 v, v ss = ?5 v 0.001 9 a
ad5544/ad5554 data sheet rev. g | page 4 of 24 parameter symbol test condition/comments min typ max unit power dissipation p diss logic inputs = 0 v 1.25 mw power supply sensitivity pss ? v dd = 5% 0.006 %/% ac characteristics 4 output voltage settling time t s to 0.1% of full scale, data = 0x0000 to 0xffff to 0x0000 0.9 s r eference multiplying bandwidth (bw) bw ? 3 db v ref x = 5 v p - p, data = 0xffff, c fb = 2.0 pf, 12 mhz dac glitch impulse q v ref x = 8 v, data = 0x0000 to 0x8000 to 0x0000 ? 1 nv - sec feedthrough error v out x/v ref x data = 0x0000, v ref x = 100 mv rms, f = 10 0 khz ? 65 db crosstalk error v out a/v ref b data = 0x0000, v ref b = 100 mv rms, adjacent channel, f = 100 khz ? 90 db digital feedthrough q cs = 1, f clk = 1 mhz 0.6 nv - sec total harmonic distortion thd v ref x = 5 v p - p, data = 0xffff, f = 1 khz ? 98 db output spot noise voltage e n f = 1 khz, bw = 1 hz 7 nv/ hz 1 all static performance tests (except i out x ) are performed in a closed - loop system using an external precision op177 i - to - v converter amplifier. the ad5544 r fb terminal is tied to the amplifier output. typical values represent average readings measured at 25 c. 2 these parameters are guaranteed by design and not subject to production testing. 3 all input contro l signals are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. 4 all ac characteristic tests are performed in a closed - loop system using an ad8038 i - to - v converter am plifier . ad5554 e lectrical c haracteristics v dd = 2.7 v to 5 .5 v, v ss = 0 v, i out x = virtual gnd, a gnd x = 0 v, v ref a = v ref b = v ref c = v ref d = 10 v, t a = full operating temperature range of ?40c to +125c , unless otherwise noted. table 2 . parameter symbol test condition /comments min typ max unit static performance 1 resolution n 1 lsb = v ref x /2 14 = 610 v when v ref x = 10 v 14 bits relative accuracy inl 0.5 lsb differential nonlinearity dnl 1 lsb output leakage current i out x data = 0x 0000, t a = 25c 10 na data = 0x 0000, t a = 8 5c 20 na full - scale gain error g fse data = 0x 3fff 2 10 mv full - scale tempco 2 tcv fs 1 ppm/c feedback resistor r fb x v dd = 5 v 4 6 8 k ? reference input v ref x range v ref x ? 15 +15 v input resistance r ref x 4 6 8 k ? input resistance match r ref x channel - to - channel 1 % input capacitance 2 c ref x 5 pf analog output output current i out x data = 0x3fff 1.25 2.5 ma output capacitance 2 c out x code dependent 80 pf logic input and output logic input low voltage v il 0.8 v logic input high voltage v ih 2.4 v input leakage current i il 1 a i nput capacitance 2 c il 10 pf logic output low voltage v ol i ol = 1.6 ma 0.4 v logic output high voltage v oh i oh = 100 a 4 v interface timing 2 , 3 clock width high t ch 25 ns clock width low t cl 25 ns cs to clock setup t css 0 ns clock to cs hold t csh 25 ns
data sheet ad5544/ad5554 rev. g | page 5 of 24 parameter symbol test condition /comments min typ max unit clock to sdo propagation delay t pd 2 20 ns load dac pulse width t ldac 25 ns data setup t ds 20 ns data hold t d h 20 ns load setup t lds 5 ns load hold t ldh 25 ns supply characteristics power supply range v dd range 2.7 5.5 v positive supply current i dd logic inputs = 0 v 5 a negative supply current i ss logic inputs = 0 v, v ss = ? 5 v 0.001 9 a power dissipation p diss logic inputs = 0 v 1.25 mw power supply sensitivity pss ? v dd = 5% 0.006 %/% ac characteristics 4 output voltage settling time t s to 0.1% of full scale, data = 0x 0000 to 0x 3fff to 0x 0000 0.9 s refe rence multiplying bandwidth (bw) bw ? 3 db v ref x = 5 v p - p, data = 0xffff, c fb = 2. 0 pf 12 mhz dac glitch impulse q v ref x = 8 v, data = 0x 0000 to 0x 2000 to 0x 0000 ? 1 nv -s ec feedthrough error v out x /v ref x data = 0x 0000, v ref x = 100 mv rms, f = 100 khz ? 65 db crosstalk error v out a/v ref b data = 0x 0000, v ref b = 100 mv rms, adjacent channel, f = 100 khz ? 90 db digital feedthrough q cs = 1, f clk = 1 mhz 0.6 nv -s ec total harmonic distortion thd v ref x = 5 v p - p, data = 0x 3fff, f = 1 khz ? 9 8 db output spot noise voltage e n f = 1 khz, bw = 1 hz 7 nv / hz 1 all static performance tests (except i out ) are performed in a closed - loop system using an external precision op177 i - to - v converter amplifier. the ad5554 r fb terminal is tied to the amplifier output. typical values represent average readings measured at 25 c. 2 these parameters are guaranteed by design and not subject to production testing. 3 all input control signals are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage le vel of 1.5 v. 4 all ac characteristic tests are performed in a closed - loop system using an ad8038 i - to - v converter amplifier,.
ad5544/ad5554 data sheet rev. g | page 6 of 24 timing diagrams t ldh t lds t ldac t csh t pd t cl t ch t dh t ds t css sdi clk cs ldac sdo input reg ld a1 a0 d15 d14 d13 d12 d11 d10 d1 d0 00943-004 figure 3. ad5544 timing diagram t ldh t lds t ldac t csh t pd t cl t ch t dh t ds t css sdi clk sdo input reg ld a1 a0 d13 d12 d11 d10 d09 d08 d1 d0 cs ldac 00943-005 figure 4. ad5554 timing diagram
data sheet ad5544/ad5554 rev. g | page 7 of 24 absolute maximum rat ings table 3 . parameter rating v dd to gnd ? 0.3 v, +8 v v ss to gnd +0.3 v, ? 7 v v ref x to gnd ? 18 v, +18 v logic input and output to gnd ? 0.3 v, +8 v v(i out x ) to gnd ? 0.3 v, v dd + 0.3 v a gnd x to dgnd ? 0.3 v, + 0.3 v input current to any pin except supplies 50 ma package power dissipation (t j m ax ? t a )/ ja thermal resistance ja 28- lead ssop 100c/w 32- lead lfcsp 32.5 c/w maximum junction temperature (t j m ax) 150c oper ating temperature range ? 40c to +125 c storage temperature range ? 65c to +150c lead temperature vapor phase, 60 s ec 215c infrared, 15 sec 220c stresses above those listed under absolute maximum ratings may cause permanent dama ge to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for e xtended periods may affect device reliability. esd caution
ad5544/ad5554 data sheet rev. g | page 8 of 24 pin configurations and function descriptions 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ad5544/ ad5554 top view (not to scale) a gnd a a gnd d i out a i out d v ref a v ref d r fb ar fb d msb dgnd v ss v dd a gnd f clk sdo sdi nc r fb b r fb c v ref b v ref c i out b i out c a gnd ba gnd c nc = no connect ldac cs rs 00943-003 figure 5. tssop pin configuration notes 1. nc = no conne c t. 2 . connect exposed pad to agnd. 24 dgnd 23 v ss 22 a gnd f 21 ldac 20 sdo 19 nc 18 r fb c 17 v ref c 1 2 3 4 5 6 7 8 a gnd a i out a v ref a r fb a msb rs v dd cs 9 10 11 12 13 14 15 16 clk sdi r fb b v ref b i out b a gnd b a gnd c i out c 32 31 30 29 28 27 26 25 nc nc nc nc a gnd d i out d v ref d r fb d ad5544 top view (not to scale) 00943-035 figure 6. lfcsp pin configuration table 4. pin function descriptions tssop pin no. lfcsp pin no. mnemonic description 1 1 a gnd a dac a analog ground. 2 2 i out a dac a current output. 3 3 v ref a dac a reference voltage input terminal. establishes dac a full-scale output voltage. this pin can be tied to the v dd pin. 4 4 r fb a establish the voltage output for dac a by co nnecting to an external amplifier output. 5 5 msb msb bit. set pin during a reset pulse (rs ) or at system power-on if tied to ground or v dd . 6 6 rs reset pin, active low input. input registers and dac registers are set to all 0s or half-scale code (0x8000 for the ad5544 and 0x2000 for the ad5554 ), determined by the voltage on the msb pin. register data = 0x0000 when msb = 0. 7 7 v dd positive power supply input. specified range of operation: 5 v 10%. 8 8 cs chip select, active low input. disables shift register loading when high. transfers serial register data to the input register when cs /ldac returns high. does not affect ldac operation. 9 9 clk clock input. positive edge cl ocks data into the shift register. 10 10 sdi serial data input. input data loads directly into the shift register. 11 11 r fb b establish the voltage output for dac b by co nnecting to an external amplifier output. 12 12 v ref b dac b reference voltage input terminal. establishes dac b full-scale output voltage. this pin can be tied to the v dd pin. 13 13 i out b dac b current output. 14 14 a gnd b dac b analog ground. 15 15 a gnd c dac c analog ground. 16 16 i out c dac c current output. 17 17 v ref c dac c reference voltage input terminal. establishes dac c full-scale output voltage. this pin can be tied to the v dd pin. 18 18 r fb c establish the voltage output for dac c by co nnecting to an external amplifier output. 19 19 nc no connect. leave the pin unconnected. 20 20 sdo serial data output. input data loads directly into the shift register. data appears at sdo at 19 clock pulses for the ad5544 and 17 clock pulses for the ad5554 after input at the sdi pin. 21 21 ldac load dac register strobe, level sensitive active low. transfers all input register data to dac registers. asynchronous active low inp ut. see table 8 and table 9 for operation. 22 22 a gnd f high current analog force ground. 23 23 v ss negative bias power supply in put. specified range of operation: ?5.5 v to +0.3 v. 24 24 dgnd digital ground pin. 25 25 r fb d establish the voltage output for dac d by co nnecting to an external amplifier output.
data sheet ad5544/ad5554 rev. g | page 9 of 24 tssop pin no. lfcsp pin no. mnemonic description 26 26 v ref d dac d reference voltage input terminal. establishes dac d full - scale output voltage. this pin can be tied to the v dd pin. 27 27 i out d dac d current output. 28 28 a gnd d dac d analog ground. n/a 29 nc do not connect. n/a 30 nc do not connect. n/a 31 nc do not connect. n/a 32 nc do not connect. n/a 33 epad connect the exposed pad to agnd x .
ad5544/ad5554 data sheet rev. g | page 10 of 24 typical performance characteristics 0.10 0 ?0.05 ?0.10 ?0.15 ?0.20 ?0.25 ?0.30 ?0.35 ?0.40 0 10,000 30,000 50,000 70,000 00943-006 dnl error (lsb) code 0.05 20,000 40,000 60,000 figure 7. ad5544 dnl vs. code , t a = 25c 0.20 0.15 0.10 0.05 0 ?0.05 ?0.10 ?0.15 ?0.20 0 4000 10,000 14,000 18,000 00943-007 inl error (lsb) code 8000 12,000 16,000 2000 6000 figure 8. ad5554 inl vs. code, t a = 25c 0.10 0.05 0 ?0.05 ?0.10 ?0.15 0 4000 10,000 14,000 18,000 00943-008 dnl error (lsb) code 8000 12,000 16,000 2000 6000 figure 9. ad5554 dnl vs. code, t a = 25c ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 ?2000 ?1500 ?1000 ?500 0 500 1000 1500 2000 0xf000 0x8000 0x7fff 0x0fff 00943-009 offset voltage ( v) inl (lsb) v dd = 5v v ref = 10v figure 10 . ad5544 integral nonlinearity error vs. op amp offset ?1.00 ?0.75 ?0.50 ?0.25 0 0.50 0.25 0.75 1.00 ?1000 ?750 ?500 ?250 0 250 500 750 1000 0xf000 0x8000 0x0fff 00943-0 1 1 op amp offset ( v) dnl (lsb) v dd = 5v v ref = 10v figure 11 . ad5544 differential nonlinearity error vs. op amp offset ?1500 ?1000 ?500 0 500 1000 1500 ?20 ?15 ?10 ?5 0 5 10 00943-013 op amp offset ( v) gain error (lsb) v dd = 5v v ref = 10v figure 12 . ad5544 gain error vs. op amp offset
data sheet ad5544/ad5554 rev. g | page 11 of 24 0.4 0.5 0.6 0.7 0.9 1.0 1.1 1.2 0.8 time (s) v out (v) 00943?012 ?4.08 ?4.06 ?4.04 ?4.02 ?4.00 ?3.98 ?3.96 ?3.94 ?3.92 ?3.90 ?3.88 figure 13 . ad5544 midscale transition 00943- 018 5v/div v dd = 5v v ref = 10v v out ldac fig ure 14 . ad5544 large signal settling time ?0.2 ?0.1 0 0.1 ?20 ?16 ?12 ?8 ?4 0 4 ?2 2 0 4 6 8 10 00943-019 time ( s) v out (v) ldac (v) figure 15 . ad5544 small signal settling time 10,000 1000 100 10 1 1k 100m 10k i dd (a) 100k 1m 10m clock frequency (hz) zero scale midscale full scale 0x5555 00943-015 figure 16 . ad5544 power supply current vs. clock frequency 0 10 20 30 40 50 60 70 80 90 100 100 1k 10k 100k 1m 00943-020 frequency (hz) psrr (db) v dd = 5v v ref = 10v figure 17 . ad5544 / ad5554 p ower supply rejection vs. frequency 20 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 0 5k 10k 15k 20k 25k frequency (hz) power spectrum (db) 00943- 1 18 figure 18 . ad5544 / ad5554 analog thd
ad5544/ad5554 data sheet rev. g | page 12 of 24 0 50 100 150 200 250 300 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 logic input (v) supply current (a) 00943-017 figure 19 . ad5544 / ad5554 power supply current vs. logic input voltage
data sheet ad5544/ad5554 rev. g | page 13 of 24 theory of operation the ad5544 and the ad5554 contain four 16-bit and 14-bit, current output dacs, respectively. each dac has its own inde- pendent multiplying reference input. both the ad5544 and the ad5554 use a 3-wire, spi-compatible serial data interface, with a configurable asynchronous rs pin for half-scale (msb = 1) or zero-scale (msb = 0) preset. in addition, an ldac strobe enables 4-channel, simultaneous updates for hardware synchronized output voltage changes. digital-to-analog converter (dac) each part contains four current-steering r-r ladder dacs. figure 20 shows a typical equivalent dac. each dac contains a matching feedback resistor for use with an external i-to-v converter amplifier. the r fb x pin connects to the output of the external amplifier. the i out x terminal connects to the inverting input of the external amplifier. the a gnd x pin should be kelvin- connected to the load point, requiring full 16-bit accuracy. these dacs are designed to operate with both negative and positive reference voltage. the v dd power pin is used only by the logic to drive the dac switches on and off. note that a matching switch is used in series with the internal 5 k feedback resistor. if users attempt to measure the value of r fb , power must be applied to v dd to achieve continuity. an additional v ss bias pin is used to guard the substrate during high temperature applications, minimizing zero-scale leakage currents that double every 10c. the dac output voltage is determined by v ref and the digital data (d) in the following equations: ?? 5544adthefor 536,65 d vv ref out ??? (1) ?? 5554adthefor 384,16 d vv ref out ??? (2) note that the output polarity is opposite the v ref polarity for dc reference voltages. v ref x v ss dgnd v dd r fb x i out x a gnd f a gnd x rr r 2r 2r 2r 5k ? s1 s2 from other dacs a gnd r 00943-025 digital interface connections omitted for clarity. switches s1 and s2 are closed, and v dd must be powered. figure 20. typical equivalent dac channel these dacs are also designed to accommodate ac reference input signals. both the ad5544 and the ad5554 accommodate input reference voltages in the range of ?15 v to +15 v. the reference voltage inputs exhibit a constant nominal input resistance of 5 k 30%. on the other hand, the i out a, i out b, i out c, and i out d dac outputs are code dependent and produce various output resistances and capacitances. the choice of external amplifier should take into account the variation in impedance generated by the ad5544/ ad5554 on the inverting input node of the amplifier. the feedback resistance, in parallel with the dac ladder resistance, dominates output voltage noise. for multiplying mode applications, an external feedback compensation capacitor, c fb , may be needed to provide a critically damped output response for step changes in reference input voltages. figure 21 shows the gain vs. frequency performance at various attenuation settings using a 23 pf external feedback capacitor connected across the i out x and r fb x terminals for the ad5544 and the ad5554 , respectively. to maintain good analog performance, power supply bypassing of 0.01 f, in parallel with 1 f, is recommended. under these conditions, a clean power supply with low ripple voltage capability should be used. switching power supplies is usually not suitable for this application due to the higher ripple voltage and pss frequency-dependent charac- teristics. it is best to derive the supply of the ad5544 / ad5554 from system analog supply voltages. do not use the digital supply (see figure 22). 00943-026 frequency (hz) gain (db) 2 0 ?2 ?4 ?6 ?8 100k 1m 10m 100m figure 21. ad5554 reference multiplying bandwidth vs. code
ad5544/ad5554 data sheet rev. g | page 14 of 24 v ref x v ss dgnd v dd r fb x i out x a gnd f a gnd x rr r r 2r 2r 2r 5k ? s1 s2 from other dacs a gnd ad5544 + a1 15v v ee v cc v out load 2r r 5v 15v analog power supp l y + 00943-028 digi t a l inter f ace connections omitted. for clarit y switches s1 and s2 are closed, and v dd must be powered. figure 22 . recommended kelvin - sensed hookup
data sheet ad5544/ad5554 rev. g | page 15 of 24 serial data interface the ad5544 / ad5554 use a 3 - wire ( cs , sdi, clk) , spi - compa tible serial data interface. serial data of the ad5544 / ad5554 is clocked into the serial input register in an 18 - bit and 16 - bit data - word format , respectively. the msb bits are loaded first. table 5 defines the 18 data - word bits for the ad5544 , and table 6 defines the 16 data - word bits for the ad5554 . data is placed on the sdi pin and clock ed into the register on the positive clock edge of clk , subject to the data s etup and data hold time requirements specified in the in terface timing specifications (see table 1 and table 2 ) . d ata can be clocked in only while the cs chip select pin is active low. for the ad5544 , only the last 18 bits clocked into the serial register are interrogated when the cs pin returns to the logic high state; extra data bits are ignored. for the ad5554 , only the last 16 bits clocked into the serial register are inter rogated when the cs pin returns to the logic high state. because most microcon - trollers output serial d ata in 8 - bit bytes, three right - justified data bytes can be written to the ad5544 . keeping the cs line low between the first, second, and third by te trans fers result s in a successful serial regist er update. similarly, two right - justified data bytes can be written to the ad5554 . keeping the cs line low between the first and second byte transfer result s in a successful serial register update. when the data is properly aligned in the shift register, the posi - tive edge of the cs initiates the transfer of new data to the target dac register, determined by the decoding of ad dress bit a1 and address bit a0. for the ad55 4 4 , table 5 , table 7 , table 8 , and figure 3 define the characteristics of the software serial interface. for the ad5554 , table 6 , table 7 , table 9 , and figure 4 define the characteristics of the software serial interface. figure 23 and figure 24 show the equivalent logic interface for the key digital control pins for the ad5544 . the ad5554 has a similar configu - ra tion, except that it has 14 data bits. two additional pins, rs and msb, provide hardware control over the preset function and dac register loading. if these functions are not needed, the rs pin can be tied to logic high. the asynchronous input rs pin forces all input and the dac registers to either the zero - code state (msb = 0) or the half - scale s tate (msb = 1). table 5 . ad5544 serial input register data format (d ata is loaded in the msb - first format ) 1 msb lsb b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 only the last 18 bits of data clo cked into the serial register (a ddress + d ata) a re inspected when the positive edge of the cs line returns to logic high. at this point , an internally generated load strobe transfers the serial register data contents (bit d15 to bit d0) to the decoded dac input reg ister address determi ned by bit a1 and bit a0. any extra bits clocked into the ad5544 s hift register are ignored; only the last 18 bits clocked in are used. if double - buffered data is not needed, the ldac pin can be tied logic low to disable the dac registers . table 6 . ad5554 serial input register data format ( data is loaded in the msb - first format ) 1 msb ls b b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 a1 a0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 only the last 16 bits of data clo cked into the serial register (a ddress + d ata) are inspected when the positive edge of the cs line returns to logic high. at this point , an internally generated load strobe transfers the serial registe r data contents (bit d13 to bit d0) to the decoded dac input register address determined by bit a1 and bit a0. any extra bits clocked into the ad 5554 shift register are ignored; only the last 16 bits clocked in are used. if double - buffered data is not need ed, the ldac pin can be tied logic low to disable the dac registers. table 7 . address decode a1 a0 dac decoded 0 0 dac a 0 1 dac b 1 0 dac c 1 1 dac d
ad5544/ad5554 data sheet rev. g | page 16 of 24 truth tables table 8 . ad5544 1 control logic truth table cs clk ldac rs msb 2 serial shift register function 3 input register function dac register high x high high x no effect latched latched low low high high x no effect latched latched low ? + 3 high high x shift register data advanced one bit latched latched low high high high x no effect latched latched ? + 3 low high high x no effect selected dac updated with current shif t register contents 4 latched high x low high x no effect latched transparent high x high high x no effect latched latched high x ? + 3 high x no effect latched latched high x high low 0 no effect latched data = 0x0000 l atched data = 0x0000 high x high low high no effect latched data = 0x8000 latched data = 0x8000 1 f or the ad5544 , data appears at the sdo p in 19 clock pulses after input at the sdi pin. 2 x = dont care. 3 ? + is a positive logic transition. 4 at power - on, both the input register and the dac register are loaded with all 0 s . table 9 . ad5554 1 control logic truth table cs clk ldac rs msb 2 serial shift register function 3 input register function 3 dac register high x high high x no effect latched latched low l high high x no effect latched latched low ? + 3 high high x shift register data advanced one bit latched latched low high high high x no effect latched latched ? + 3 low high high x no effect selected dac updated with current shif t register contents 4 latched high x low high x no effect latched transparent high x high high x no effect latched latched high x ? + 3 high x no effect latched latched high x high low 0 no effect latched data = 0x0000 l atched data = 0x0000 high x high low high no effect latched d ata = 0x2000 latched data = 0x2000 1 for the ad5554 , data appears at the sdo p in 17 clock pulses after input at the sdi pin . 2 x = dont care. 3 ? + is a positive logic transition. 4 at power - on, both the input register and the dac register are loaded with all 0 s .
data sheet ad5544/ad5554 rev. g | page 17 of 24 i nput register r i nput register r i nput register r i nput register r dac a b c d 2:4 d ecode d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d1 1 d12 d13 d14 d15 a0 a1 en 16 d ac d register r d ac c register r d ac b register r d ac a register r p ower- on reset d ac b d ac c d ac d d ac a ad5544 v ref a b c d v dd r fb a i out a a gnd a r fb b i out b a gnd b r fb c i out c a gnd c r fb d i out d a gnd d a gnd f dgnd ms b v ss set ms b set ms b sdo sdi clk cs rs ldac 00943-029 figure 23 . system level digital interfacing en shift register address decode r a b c d t o input register 19 th /17 th clock sdo sdi clk cs 00943-030 figure 24 . ad5544 / ad5554 equivalent logic interface power - on reset when the v dd power supply is turned on, an internal reset strobe forces all the input and dac registers to the zero - code state or half - scale state, depen ding on the msb pin voltage. the v dd power supply should have a smooth positive ramp without drooping to have consistent results, especially in the region of v dd = 1.5 v to 2.3 v. the v ss supply has no effect on the power - on reset perform - ance. the dac reg ister data stay s at a zero - scale or half - scale setting until a valid serial register data load takes place. esd protection circu its all logic input pins contain back - biased esd protection zener diode s that are connected to ground (dgnd) and v dd , as shown i n figure 25. v dd d igi t a l i nputs 5k ? dgnd 00943-031 figure 25 . equivalent esd production circuits power supply sequenc e as standard practice, it is recommended that v dd , v ss , and ground be powered up prior to any reference. the ideal power - u p sequence is as follows: a gnd x , d gnd , v dd , v ss , v ref x , and the digital inputs. a noncompli ance power - up sequence may elevate the reference current, but the devices resume normal operation once v dd and v ss are powered up.
ad5544/ad5554 data sheet rev. g | page 18 of 24 layout and power supply bypassing it is good practice to employ a compact, minimum lead length layout design. the leads to the input should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with 0.01 f to 0.1 f disc or chip ceramic capacitors. low esr 1 f to 10 f tantalum or electrolytic capaci- tors should also be applied at v dd to minimize any transient disturbance and filter any low frequency ripple (see figure 26). users should not apply switching regulators for v dd due to the power supply rejection ratio (psrr) degradation over frequency. a gnd x v ss dgnd ad5544/ad555 4 0 0943-032 v dd c3 10 f + c1 0.1 f c4 10 f c2 0.1 f v ss v dd figure 26. power supply bypassing and gr ounding connection grounding the dgnd and a gnd x pins of the ad5544 / ad5554 serve as digital and analog ground references. to minimize the digital ground bounce, the dgnd terminal should be joined remotely at a single point to the analog ground plane (see figure 26).
data sheet ad5544/ad5554 rev. g | page 19 of 24 applications information the ad5544 / ad5554 are , inherently , two - qua drant multiplying dacs . that is, they can be easily set up for unipolar output operation. the full - scale output polarity is the inverse of the reference inp ut voltage. in some applications , it may be necessary to generate the full four - quadrant multiplying capability or a bipolar output swing. this is easily accomplished using an additional external ampli - fier (a2) configured as a summing amplifier (see figure 27 ). a2 a1 one channe l ad5544 i out x r fb x v ref x v dd v ss a gnd f a gnd x v out 10k ? 10k ? 5k ? ad588 v ref 10v d igital interface connections omitted for clarity. ? 10v < v out < +10v 00943-0-033 figure 27 . four - quadrant multiplying application circuit in this circuit , the first and second amplifiers (a1 and a2) provide a total gain of 2 , which increases the output voltage span to 20 v. biasing the external amplifier wi th a 10 v offset from the refer ence voltage results in a full four - quadrant multiplying circuit. the transfer equation of this circuit shows that both negative and positive output voltages are created as the input data (d) is incremented from code zero (v out = ? 10 v) to midscale (v out = 0 v) to full scale (v out = 10 v). ( ) 5544 ad the for 1 768 , 32 ref out v d v ? ? ? ? ? ? ? ? (3) ( ) 5554 ad the for 1 8192 ref out v d v ? ? ? ? ? ? ? ? (4) reference selection when selecting a reference for use with the ad55xx series of current output dacs, pay attention to the output volta ge, temperature coefficient specification of the reference. choosing a precision reference with a low output temperature coefficient minimizes error sources . table 10 lists some of the references available from analog devices, i nc., that are suitable for use with this range of current output dacs. amplifier selection the primary requirement for the current - steering mode is an amplifier with low input bias currents and low input offset voltage. because of the code - dependent output resistance of the dac, th e input offset voltage of an op amp is multiplied by the variable gain of the circuit. a change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifiers input of fset voltage. this output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential linearity error, which, if large enough, can cause the dac to be nonmonotonic. the input bias current of an op amp also generates an offset at the voltage output because of the bias current flowing in the feedback resistor, r fb . common - mode rejection of the op amp is important in voltage - switching circuits because it produces a code - dependent error at the voltage output of the circuit. provided that the dac switches are driven from true wideband , low impedance sources (v in and agnd), they settle quickly. consequently, the slew rate and settling time of a voltage - switching dac circuit is determined largely by the o utput op amp. to obtain minimum settling time in this configuration, minimize capacitance at the v ref node (the voltage output node in this application) of the dac. this is done by using low input capacitance buffer amplifiers and careful board design. ana log devices offers a wide range of amplifiers for both precision dc and ac applications, as listed in table 11 and table 12.
ad5544/ad5554 data sheet rev. g | page 20 of 24 table 10. suitable analog devices precision references part no. output voltage (v) initial tolerance (%) maximum temperature drift (ppm/c) i ss (ma) output noise (v p-p) package(s) adr01 10 0.05 3 1 20 soic-8 adr01 10 0.05 9 1 20 tsot-5, sc70-5 adr02 5.0 0.06 3 1 10 soic-8 adr02 5.0 0.06 9 1 10 tsot-5, sc70-5 adr03 2.5 0.1 3 1 6 soic-8 adr03 2.5 0.1 9 1 6 tsot-5, sc70-5 adr06 3.0 0.1 3 1 10 soic-8 adr06 3.0 0.1 9 1 10 tsot-5, sc70-5 adr420 2.048 0.05 3 0.5 1.75 soic-8, msop-8 adr421 2.50 0.04 3 0.5 1.75 soic-8, msop-8 adr423 3.00 0.04 3 0.5 2 soic-8, msop-8 adr425 5.00 0.04 3 0.5 3.4 soic-8, msop-8 adr431 2.500 0.04 3 0.8 3.5 soic-8, msop-8 adr435 5.000 0.04 3 0.8 8 soic-8, msop-8 adr391 2.5 0.16 9 0.12 5 tsot-5 adr395 5.0 0.10 9 0.12 8 tsot-5 table 11. suitable analog devices precision op amps part no. supply voltage (v) v os maximum (v) i b maximum (na) 0.1 hz to 10 hz noise (v p-p) supply current (a) package(s) op97 2 to 20 25 0.1 0.5 600 soic-8, pdip-8 op1177 2.5 to 15 60 2 0.4 500 msop-8, soic-8 ad8675 5 to 18 75 2 0.1 2300 msop-8, soic-8 ad8671 5 to 15 75 12 0.077 3000 msop-8, soic-8 ada4004-1 5 to 15 125 90 0.1 2000 soic-8, sot-23-5 ad8603 1.8 to 5 50 0.001 2.3 40 tsot-5 ad8607 1.8 to 5 50 0.001 2.3 40 msop-8, soic-8 ad8605 2.7 to 5 65 0.001 2.3 1000 wlcsp-5, sot-23-5 ad8615 2.7 to 5 65 0.001 2.4 2000 tsot-5 ad8616 2.7 to 5 65 0.001 2.4 2000 msop-8, soic-8 table 12. suitable analog devices high speed op amps part no. supply voltage (v) bw at acl (mhz) slew rate (v/s) v os (max) (v) i b (max) (na) package(s) ad8065 5 to 24 145 180 1500 0.006 soic-8, sot-23-5 ad8066 5 to 24 145 180 1500 0.006 soic-8, msop-8 ad8021 5 to 24 490 120 1000 10,500 soic-8, msop-8 ad8038 3 to 12 350 425 3000 750 soic-8, sc70-5 ada4899-1 5 to 12 600 310 35 100 lfcsp-8, soic-8 ad8057 3 to 12 325 1000 5000 500 sot-23-5, soic-8 ad8058 3 to 12 325 850 5000, 500 soic-8, msop-8 ad8061 2.7 to 8 320 650 6000 350 sot-23-5, soic-8 ad8062 2.7 to 8 320 650 6000 350 soic-8, msop-8 ad9631 3 to 6 320 1300 10,000 7000 soic-8, pdip-8
data sheet ad5544/ad5554 rev. g | page 21 of 24 outline dimensions compliant to jedec standards mo-150-ah 060106-a 28 15 14 1 10.50 10.20 9.90 8.20 7.80 7.40 5.60 5.30 5.00 seating plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarity 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 28. 28-lead shrink small outline package [ssop] (rs-28) dimensions shown in millimeters compliant to jedec standards mo-220-whhd. 1 0.50 bsc 3.50 ref bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r 3.65 3.50 sq 3.45 s eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min 04-02-2012-a figure 29. 32-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp-32-11) dimensions shown in millimeters
ad5544/ad5554 data sheet rev. g | page 22 of 24 ordering guide model 1 res bit inl lsb dnl lsb temperature range package description package option ad5544ars 16 2 1 .5 ? 40c to +125c 28- lead shrink small outli ne package [ssop] rs -28 ad5544arsz 16 2 1 .5 ? 40c to +125c 28- lead shrink small outline package [ssop] rs -28 ad5544arsz - reel7 16 2 1.5 ?40c to +125c 28- lead shrink small outline package [ssop] rs -28 ad5544brsz 16 1 1 ?40c to +125c 28- lead shr ink small outline package [ssop] rs -28 ad5544brsz - reel7 16 1 1 ?40c to +125c 28- lead shrink small outline package [ssop] rs -28 ad5544acpz -1 -r2 16 4 1 ?40c to +125c 32- lead lfcsp_wq cp -32-11 ad5544acpz -1 - rl7 16 4 1 ?40c to +125c 32- lead lfcsp _wq cp -32-11 ad5544bcpz -r2 16 1 1 ?40c to +125c 32- lead lfcsp_wq cp -32-11 ad5544bcpz -rl7 16 1 1 ?40c to +125c 32- lead lfcsp_wq cp -32-11 ad5554brsz 14 0.5 1 ?40c to +125c 28- lead shrink small outline package [ssop] rs -28 ev - ad5544 /45 sdz evaluation board 1 z = rohs compliant part.
data sheet ad5544/ad5554 rev. g | page 23 of 24 notes
ad5544/ad5554 data sheet rev. g | page 24 of 24 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors) . ? 2000 C 2013 analog devices, inc. all righ ts reserved. trademarks and registered trademarks are the property of their respective owners. d00943 - 0 - 5/13(g)

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